The largest contract manufacturer of semiconductor chips that the company unveiled at the technology Symposium in Santa Clara, California, has introduced a new technology to double the performance of graphics cards.
Now each GPU is produced on a thin silicon wafer on which a special technical method of forming an array of semiconductor elements, and at the last stage of metallized copper. The more complex the processor, the more transistors and other elements, the more the chip itself.
Until recently, the area of the chips has grown rapidly that was possible to restrain decrease in the size of semiconductor elements. In recent years, the process technology when production decreased from 90 to 5 nanometers, but now most of the chips use a technology from 7 to 14 nanometer, 5 nanometer products only come from experienced laboratories.
The manufacturers will be extremely difficult to go further due to physical constraints of the crystal lattice of silicon. In other words, progress came to the moment of the end of the race for nanometers. Modern graphics chips are also products of the highly complex and comprise from 6 to 12 billion transistors. It will be very difficult to continue to increase their capacity at the same pace.
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Anticipating this, TSMC has offered a technology called “plate in plate” (wafer-on-wafer), which is somewhat similar to the technology on which now produce 3D NAND memory. The idea is that on a single wafer of silicon to another place, connect them together using the well established method of flip-chip mounting, wherein the upper plate contains more silicon transitions for switching from the previous layer.
Partners TSMC from the company Cadence say that now the Taiwanese manufacturer showed a number of customers this technology on the example of two plates. However, their number can be more, and all plates, except the first, are connected through the silicon transitions.
This decision will give a great increase in performance, in some cases reaching 100 %. First, the reduced distance between the edges of the chip, the engineers will be able to place blocks closer to each other.
Second, it is not necessary to design several different families for different market segments — budget, mid, high and top, pulling the blocks from the top of the architecture. You can do architecture for the middle market and promote it on the market productive solutions by adding two or three layers.
The only requirement is that you need to take to implement this technology — extremely low reject rate. The source claims that if one of the plates in the layer will be defective, the entire chip will have to go. It will not allow you to use the technology for the production of budget decisions. You will also need to use a technical process to 16 nanometers, which gives an acceptable level of marriage.
По материалам: vgtimes.ru